What is Sigma Delta type ADC?

What is Sigma Delta type ADC?

The design of delta-sigma (∆Σ) analog-to- digital converters (ADCs) is approximately three-quarters digital and one-quarter analog. Basically, these converters consist of an oversampling modulator followed by a digital/ decimation filter that together produce a high-resolution data-stream output.

What is a Sigma Delta DAC?

A delta-sigma DAC encodes a high-resolution digital input signal into a lower-resolution but higher sample-frequency signal that is mapped to voltages, and then smoothed with an analog filter. For example, the Super Audio CD (SACD) stores the output of a delta-sigma modulator directly on a disk.

What is meant by phase-locked loop PLL circuit?

A phase-locked loop (PLL) is an electronic circuit with a voltage or voltage-driven oscillator that constantly adjusts to match the frequency of an input signal. PLLs are used to generate, stabilize, modulate, demodulate, filter or recover a signal from a “noisy” communications channel where data has been interrupted.

What is the use of Sigma Delta ADC?

Several applications for Delta-Sigma converters are included. Modern Sigma-delta converters offer high resolution, high integration, low power consumption, and low cost, making them a good ADC choice for applications such as process control, precision temperature measurements, and weighing scales.

What is a phase locked loop used for?

Phase locked loops are closed-loop feedback systems consisting of both analog and digital components including a voltage controlled oscillator. They are used for the generation of an output signal the frequency of which (or that of a signal derived from it) is synchronized (or locked) to that of a reference input.

What is the principle of PLL?

The input signal is directly proportional to the output frequency of the VCO (fo). The input and output frequencies are compared and adjusted through the feedback loop until the output frequency is equal to the input frequency. Hence, the PLL works like free running, capture, and phase lock.

What is the frequency of a sigma delta ADC?

This PLL design is specifically intended for Continuous-Time Sigma-Delta ADC operating at 640MHz frequency which is an important component of ICs used in electronics and communication devices whose clock rates and timing relationships are vital.

How are phase locked loops used in digital clocks?

To reliably receive the high-speed data, PLL provides a solution. PLL locks the clock phase that samples the data to the phase of the input data. Within the digital systems, well-timed clocks are generated with phase-locked loops (PLLs).

What is the lock in time for ADC clock generator?

This work has a lock-time of around 2.5us which is a fast lock-in value for the lock-in time of ADC clock generator. The desired output frequency which is 640 MHz is achieved on all corners ranging from 608 MHz to 672 MHz which is within 640MHz ±5% tolerance.